Device modeling for analog and RF CMOS circuit design

3.4.1 RF Measurement and De-embedding Techniques3.4.2 Parameter Extraction; 3.5 NQS Model for RF Applications; References; 4 Noise Modeling; 4.1 Noise Sources in a MOSFET; 4.2 Flicker Noise Modeling; 4.2.1 The Physical Mechanisms of Flicker Noise; 4.2.2 Flicker Noise Models; 4.2.3 Future Work in Flicker Noise Modeling; 4.3 Thermal Noise Modeling; 4.3.1 Existing Thermal Noise Models; 4.3.2 HF Noise Parameters; 4.3.3 Analytical Calculation of the Noise Parameters; 4.3.4 Simulation and Discussions; 4.3.5 Induced Gate Noise Issue; References; 5 Proper Modeling for Accurate Distortion Analysis.

5.1 Introduction5.2 Basic Terminology; 5.3 Nonlinearities in CMOS Devices and Their Modeling; 5.4 Calculation of Distortion in Analog CMOS Circuits; References; 6 The BSIM4 MOSFET Model; 6.1 An Introduction to BSIM4; 6.2 Gate Dielectric Model; 6.3 Enhanced Models for Effective DC and AC Channel Length and Width; 6.4 Threshold Voltage Model; 6.4.1 Enhanced Model for Nonuniform Lateral Doping due to Pocket (Halo) Implant; 6.4.2 Improved Models for Short-channel Effects; 6.4.3 Model for Narrow Width Effects; 6.4.4 Complete Threshold Voltage Model in BSIM4; 6.5 Channel Charge Model.

6.6 Mobility Model6.7 Source/Drain Resistance Model; 6.8 I-V Model; 6.8.1 I-V Model When rdsMod = 0 (R(DS)(V) 0); 6.8.2 I-V Model When rdsMod = 1 (R(DS)(V) = 0); 6.9 Gate Tunneling Current Model; 6.9.1 Gate-to-substrate Tunneling Current I(GB); 6.9.2 Gate-to-channel and Gate-to-S/D Currents; 6.10 Substrate Current Models; 6.10.1 Model for Substrate Current due to Impact Ionization of Channel Current; 6.10.2 Models for Gate-induced Drain Leakage (GIDL) and Gate-induced Source Leakage (GISL) Currents; 6.11 Capacitance Models; 6.11.1 Intrinsic Capacitance Models.